In recent years, an analog circuit such as a PLL circuit or a DLL circuit has been mounted on a chip.
The PLL circuit has a function of multiplying a clock frequency or performing a skew adjustment of a clock within an LSI (Large Scale Integrated circuit). The PLL circuit is an indispensable circuit for actualizing speed-up and scale-up of the LSI over the recent years.
The DLL circuit is an indispensable circuit for a DDR (Double Data Rate)-SDRAM (Synchronous Dynamic Random Access Memory). The DLL is used for generating an intended delay within the LSI.
A conventional method verifies operations of the PLL circuit or the DLL circuit as follows. Using a hardware description language such as Verilog, the PLL circuit or the DLL circuit is functionally described to perform a logic simulation (see, e.g., Japanese Laid-open Patent Publication No. 2000-357179).
FIG. 8 illustrates a configuration of a general PLL circuit (a circuit incorporating no frequency dividing circuit).
A PLL circuit 80 has a 1/k frequency dividing circuit 81, a 1/n frequency dividing circuit 82 and a PLL block 83. Each block is provided as a logic library. During the logic simulation, these blocks are connected with each other.
The 1/k frequency dividing circuit 81 frequency-multiplies a clock signal to an infrequency terminal by 1/k, and supplies a frequency-multiplied clock signal as a reference clock to a CK terminal of the PLL block 83.
The 1/n frequency dividing circuit 82 frequency-multiplies an output clock from an X terminal of the PLL block 83 by 1/n, and supplies a frequency-multiplied output clock as a feedback clock to an FB terminal of the PLL block 83. Further, the 1/n frequency dividing circuit 82 is reset according to a start reset signal supplied to an XRST terminal.
The PLL block 83 receives the reference clock from the CK terminal and, at the same time, receives the feedback clock from the FB terminal. Then, the PLL block 83 outputs from the X terminal the output clock obtained by frequency-multiplying the reference clock by n. The output clock from the X terminal is output from an OUT terminal to circuits outside the PLL circuit 80. The PLL block 83 is started or reset according to a start reset signal supplied to an S terminal. When a rise (or a fall) phase difference between the reference clock and the feedback clock falls within a predetermined range (Lock determination phase difference range), the PLL block 83 outputs a Lock signal indicating a locked state of the PLL block 83 from the Lock terminal.
A PLL block incorporating a frequency dividing circuit is another block generally used as the logic library.
FIG. 9 illustrates a configuration of a PLL circuit incorporating the frequency dividing circuit.
A PLL circuit 85 has a PLL block 86 incorporating the frequency dividing circuits as illustrated in FIG. 8. The PLL block 86 incorporates a feedback loop and therefore has no FB terminal. In the same manner as in FIG. 8, an output clock obtained by frequency-multiplying a reference clock is output from an X terminal, and further output from an OUT terminal to circuits outside the PLL circuit 85.
FIG. 10 illustrates a configuration of a general DLL circuit.
The DLL circuit 90 has a 1/k frequency dividing circuit 91, a 1/n frequency dividing circuit 92, and a DLL block 93. The 1/k frequency dividing circuit 91 and the 1/n frequency dividing circuit 92 have the same functions as those of the 1/k frequency dividing circuit 81 and 1/n frequency dividing circuit 82 of the PLL circuit 80 in FIG. 8.
The DLL block 93 incorporates the PLL block 83 illustrated in FIG. 8. The DLL block 93 outputs, from terminals DLX0 to DLX15, signals obtained by adjusting a delay amount between a reference clock and a signal (e.g., a data strobe signal of the DDR-SDRAM) supplied from a DQS terminal.
Next, the following will describe one example of an operation in conventional logic verification of a PLL circuit.
FIG. 11 illustrates a flow of a conventional logic simulation of the PLL circuit.
First, the PLL circuit 80 as illustrated in FIG. 8 receives from the S terminal a start reset signal for starting the PLL block 83, and releases a reset state of the PLL block 83. Similarly, the PLL circuit 80 receives from an XRST terminal a start reset signal for releasing a reset state of the 1/n frequency dividing circuit 82. Thus, a reset state of the PLL circuit 80 is released, and the operation is started (step S80). When starting the simulation, a peculiar (or specified) minimum oscillation frequency of the PLL block 83 is set as a frequency of the output clock from the X terminal.
Next, the PLL circuit 80 detects a frequency of the reference clock supplied to the CK terminal and, at the same time, detects a frequency of the feedback clock supplied to the FB terminal (step S81).
Then, the PLL circuit 80 detects a rise (or a fall) phase difference between the reference clock and the feedback clock (step S82).
Thereafter, the PLL circuit 80 performs multiple processing and phase adjustment processing based on the detected phase difference (step S83). In the logic simulation of the PLL circuit 80, a minimum oscillation frequency and maximum oscillation frequency, a tilt coefficient, and a Lock determination phase difference range are previously set. Thus, the conventional logic simulation is performed. Specifically, according to the tilt coefficient, the PLL circuit 80 raises or lowers the frequency of the output clock for the detected phase difference between the reference clock and the feedback clock. More specifically, when a phase of the feedback clock is leading that of the reference clock, the PLL circuit 80 recognizes that a frequency of the output clock from the X terminal of the PLL block 83 is high, and performs an operation of lowering the frequency of the output clock.
Conversely, when the phase of the feedback clock delays from that of the reference clock, the PLL circuit 80 recognizes that the frequency of the output clock from the X terminal of the PLL block 83 is low, and performs an operation of raising the frequency of the output clock.
This output clock is again supplied to the FB terminal of the PLL block 83 via the 1/n frequency dividing circuit 82, and the PLL circuit 80 repeats the processes from step S81.
During the processes, when the above-described phase difference between the reference clock and the feedback clock continues to fall within the Lock determination phase difference range as another control parameter, the PLL circuit 80 outputs the Lock signal indicating a locked state of the PLL circuit from the Lock terminal.
The conventional logic simulation method simulates the operation of the PLL circuit 80 as an analog circuit according to the above-described flow.
During the conventional logic simulation, the guaranteed frequency range of the PLL circuit is approximately from 50 to 100 MHz, and the maximum output frequency is approximately 500 MHz.
However, when the conventional logic simulation method verifies the analog circuit such as the PLL circuit or the DLL circuit, the logic operation in the logic simulation does not necessarily match an actual physical operation. In this case, there is a problem that verification errors occur to cause a failure in the actual physical operation.
This problem has become increasingly prominent in recent years where a high-frequency PLL circuit operating over a wide range of frequencies (e.g., 300 to 600 MHz) and operating at a maximum frequency of about 1.6 GHz has been demanded. As a result, the conventional logic simulation method using the tilt coefficient to perform a phase adjustment or multiple function becomes hard to verify the physical operation of the PLL circuit.